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| Integrated Circuit Systems, Inc. ICS8523 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER FEATURES * 4 differential 1.8V LVHSTL outputs * Selectable CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency up to 650MHz * Translates any single-ended input signal to 1.8V LVHSTL levels with resistor bias on nCLK input * Output skew: 30ps (maximum) * Part-to-part skew: 150ps (maximum) * Propagation delay: 1.6ns (maximum) * 3.3V core, 1.8V output operating supply * 0C to 70C ambient operating temperature * Industrial temperature information available upon request GENERAL DESCRIPTION The ICS8523 is a low skew, high performance 1-to-4 Differential-to-LVHSTL fanout buffer HiPerClockSTM and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS8523 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. ,&6 Guaranteed output and part-to-part skew characteristics make the ICS8523 ideal for those applications demanding well defined performance and repeatability. BLOCK DIAGRAM CLK_EN D Q LE CLK nCLK PCLK nPCLK 0 1 Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 PIN ASSIGNMENT GND CLK_EN CLK_SEL CLK nCLK PCLK nPCLK nc nc VDD 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Q0 nQ0 VDDO Q1 nQ1 Q2 nQ2 VDDO Q3 nQ3 CLK_SEL ICS8523 20-Lead TSSOP 6.5mm x 4.4mm x 0.92mm body package G Package Top View 8523BG www.icst.com/products/hiperclocks.html 1 REV. B JULY 31, 2001 Integrated Circuit Systems, Inc. ICS8523 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER Type Power Input Description TABLE 1. PIN DESCRIPTIONS Number 1 2 Name GND CLK_EN Power supply ground. Connect to ground. Synchronizing clock enable. When HIGH, clock outputs follow clock Pullup input. When LOW, Q outputs are forced low, nQ outputs are forced high. LVCMOS / LVTTL interface levels. Clock select input. When HIGH, selects differential PCLK, nPCLK Pulldown inputs. When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Pullup Inver ting differential clock input. Inver ting differential LVPECL clock input. No connect. Positive supply pin. Connect to 3.3V. Differential output pair. LVHSTL interface levels. Output supply pins. Connect to 1.8V. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Pulldown Non-inver ting differential LVPECL clock input. 3 4 5 6 7 8, 9 10 11, 12 13, 18 14, 15 16, 17 19, 20 CLK_SEL CLK nCLK PCLK nPCLK nc VDD nQ3, Q3 VDDO nQ2, Q2 nQ1, Q1 nQ0, Q0 Input Input Input Input Input Unused Power Output Power Output Output Output NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN Parameter CLK, nCLK Input Capacitance PCLK, nPCLK CLK_EN, CLK_SEL Input Pullup Resistor Input Pulldown Resistor 51 51 Test Conditions Minimum Typical Maximum 4 4 4 Units pF pF pF K K 8523BG www.icst.com/products/hiperclocks.html 2 REV. B JULY 31, 2001 Integrated Circuit Systems, Inc. ICS8523 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER Inputs Outputs Selected Source CLK, nCLK PCLK, nPCLK CLK, nCLK Q0 thru Q3 Disabled; LOW Disabled; LOW Enabled nQ0 thru nQ3 Disabled; HIGH Disabled; HIGH Enabled TABLE 3A. CONTROL INPUT FUNCTION TABLE CLK_EN 0 0 1 CLK_SEL 0 1 0 1 1 PCLK, nPCLK Enabled Enabled After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the CLK , nCLK and PCLK, nPCLK inputs as described in Table 3B. Disabled nCLK, nPCLK CLK, PCLK Enabled CLK_EN nQ0 - nQ3 Q0 - Q3 FIGURE 1 - CLK_EN TIMING DIAGRAM TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs CLK or PCLK 0 1 0 1 Biased; NOTE 1 nCLK or nPCLK 0 1 Biased; NOTE 1 Biased; NOTE 1 0 LOW HIGH LOW HIGH HIGH Outputs Q0 thru Q3 nQ0 thru nQ3 HIGH LOW HIGH LOW LOW Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information section on page 8, Figure 9, which discusses wiring the differential input to accept single ended levels. 8523BG www.icst.com/products/hiperclocks.html 3 REV. B JULY 31, 2001 Integrated Circuit Systems, Inc. ICS8523 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 73.2C/W -65C to 150C ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDDx Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol VDD VDDO IDD Parameter Input Power Supply Voltage Output Power Supply Voltage Power Supply Current Test Conditions Minimum 3.135 1.6 Typical 3.3 1.8 Maximum 3.465 2.0 50 Units V V mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current CLK_EN, CLK_SEL CLK_EN, CLK_SEL CLK_EN CLK_SEL CLK_EN CLK_SEL VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 Test Conditions Minimum 2 -0.3 Typical Maximum 3.765 0.8 5 150 Units V V A A A A TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK CLK nCLK CLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 1.3 VDD - 0.85 Minimum Typical Maximum 5 150 Units A A A A V V Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. 8523BG www.icst.com/products/hiperclocks.html 4 REV. B JULY 31, 2001 Integrated Circuit Systems, Inc. ICS8523 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER Test Conditions PCLK nPCLK PCLK nPCLK VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.3 1 VDD Minimum Typical Maximum 150 5 Units A A A A V V TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol IIH IIL VPP Parameter Input High Current Input Low Current Peak-to-Peak Input Voltage Common Mode Input Voltage; NOTE 1, 2 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications the maximum input voltage for PCLK and nPCLK is VDD + 0.3V. TABLE 4D. LVHSTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol Parameter Output High Voltage; VOH NOTE 1 Output Low Voltage; VOL NOTE 1 VOX VSWING Output Crossover Voltage Test Conditions Minimum 1 0 40% x (VOH - VOL) + VOL 0.75 Typical Maximum 1.4 0.4 60% x (VOH - VOL) + VOL 1.25 Units V V V V Peak-to-Peak Output Voltage Swing NOTE 1: Outputs terminated with 50 to ground. TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA = 0C TO 70C Symbol fMAX tPD Parameter Maximum Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise Time Output Fall Time 20% to 80% @ 50MHz 20% to 80% @ 50MHz 300 300 650MHz 1.3 Test Conditions Minimum Typical Maximum 650 1.6 30 150 700 700 55 Units MHz ns ps ps ps ps % t sk(o) t sk(pp) tR tF odc Output Duty Cycle 45 All parameters measured at 500MHz unless noted otherwise. The cycle to cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 8523BG www.icst.com/products/hiperclocks.html 5 REV. B JULY 31, 2001 Integrated Circuit Systems, Inc. ICS8523 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VDDO V DD SCOPE Qx LVHSTL VDD = 3.3V 5% VDDO = 1.8V 0.2V nQx GND = 0V FIGURE 2 - OUTPUT LOAD TEST CIRCUIT V DD CLK, PCLK V nCLK, nPCLK PP Cross Points V CMR GND FIGURE 3 - DIFFERENTIAL INPUT LEVEL Qx nQx Qy nQy tsk(o) FIGURE 4 - OUTPUT SKEW 8523BG www.icst.com/products/hiperclocks.html 6 REV. B JULY 31, 2001 Integrated Circuit Systems, Inc. ICS8523 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER Qx PART 1 nQx Qy PART 2 nQy tsk(pp) FIGURE 5 - PART-TO-PART SKEW 80% 80% V SWING 20% Clock Inputs and Outputs t t AND 20% R F FIGURE 6 - INPUT OUTPUT RISE AND FALL TIME CLK, PCLK nCLK, nPCLK Q0 - Q3 nQ0 - nQ3 t PD FIGURE 7 - PROPAGATION DELAY CLK, PCLK, Qx nCLK, nPCLK, nQx Pulse Width t t odc = t PW PERIOD PERIOD FIGURE 8 - odc & tPERIOD 8523BG www.icst.com/products/hiperclocks.html 7 REV. B JULY 31, 2001 Integrated Circuit Systems, Inc. ICS8523 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 9 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K CLK_IN + V_REF C1 0.1uF R2 1K FIGURE 9: SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 8523BG www.icst.com/products/hiperclocks.html 8 REV. B JULY 31, 2001 Integrated Circuit Systems, Inc. ICS8523 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8523. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8523 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 50mA = 173.3mW Power (outputs)MAX = 32mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 32mW = 128mW Total Power_MAX (3.465V, with all outputs switching) = 173.3mW + 128mW = 301.3mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = junction-to-ambient thermal resistance Pd_total = Total device power dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used . Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70C with all outputs switching is: 70C + 0.301W * 66.6C/W = 90.05C. This is well below the limit of 125C This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). Table 6. Thermal Resistance qJA for 20-pin TSSOP, Forced Convection qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2C/W 200 98.0C/W 66.6C/W 500 88.0C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8523BG www.icst.com/products/hiperclocks.html 9 REV. B JULY 31, 2001 Integrated Circuit Systems, Inc. 3. Calculations and Equations. ICS8523 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 10. VDD Q1 VOUT RL 50 FIGURE 10 - LVHSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of V - 2V. DD Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (V OH_MAX /R ) * (V L DD_MAX -V OH_MAX ) ) Pd_L = (V OL_MAX /R ) * (V L DD_MAX -V OL_MAX * * For logic high, V OUT =V OH_MAX =V DD_MAX - 1.2V - 0.4V For logic low, V OUT =V OL_MAX =V DD_MAX Pd_H = (1.2V/50) * (2V - 1.2V) = 19.2mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW 8523BG www.icst.com/products/hiperclocks.html 10 REV. B JULY 31, 2001 Integrated Circuit Systems, Inc. ICS8523 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE qJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W Multi-Layer PCB, JEDEC Standard Test Boards 73.2C/W 200 98.0C/W 66.6C/W 500 88.0C/W 63.5C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8523 is: 472 8523BG www.icst.com/products/hiperclocks.html 11 REV. B JULY 31, 2001 Integrated Circuit Systems, Inc. ICS8523 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER PACKAGE OUTLINE - G SUFFIX TABLE 8. PACKAGE DIMENSIONS SYMBOL MIN N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 20 -0.05 0.80 0.19 0.09 6.40 6.40 BASIC 4.50 1.20 0.15 1.05 0.30 0.20 6.60 Millimeters MAX Reference Document: JEDEC Publication 95, MS-153 8523BG www.icst.com/products/hiperclocks.html 12 REV. B JULY 31, 2001 Integrated Circuit Systems, Inc. ICS8523 LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER Marking ICS8523BG ICS8523BG Package 20 lead TSSOP 20 lead TSSOP on Tape and Reel Count 72 per tube 2500 Temperature 0C to 70C 0C to70C TABLE 9. ORDERING INFORMATION Part/Order Number ICS8523BG ICS8523BGT While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8523BG www.icst.com/products/hiperclocks.html 13 REV. B JULY 31, 2001 |
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